View PD78P083A_1451076.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1996 data sheet 8-bit single-chip microcontroller mos integrated circuit m m m m m pd78p083(a) the information in this document is subject to change without notice. document no. u12175ej1v0ds00 (1st edition) date published march 1997 n printed in japan description the m pd78p083(a) is a member of the m pd78083 subseries of the 78k/0 series products. comparing with the m pd78p083 (standard), more strict quality assurance programs are applied to this product (called special of the quality grade in nec). the m pd78p083(a) uses one-time prom instead of internal roms of the m pd78081(a) and m pd78082(a). because this device can be programmed by users, it is ideally suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and time- to-market of a new product. the details of functions are described in the users manuals. be sure to read the following manuals before designing. m m m m m pd78083 subseries user's manual : u12176e 78k/0 series user's manual instructions : ieu-1372 features y pin-compatible with mask rom version (except v pp pin) y internal prom: 24 kbytes note ? m pd78p083cu(a), m pd78p083gb(a): one-time programmable (ideally suited for small-scale production) y internal high-speed ram: 512 bytes note y can be operated in the same supply voltage as the mask rom version (v dd = 1.8 to 5.5 v) y corresponding to qtop tm microcontrollers (under planning) note the internal prom and internal high-speed ram capacities can be changed by setting the internal memory size switching register (ims). remarks 1. qtop microcontroller is a general term for microcontrollers which incorporate one-time prom and are totally supported by nec's programming service (from programming to marking, screening and verification). 2. for the differences between prom and mask rom versions, refer to chapter 1. differences between the m m m m m pd78p083(a) and mask rom versions . 1997
2 m pd78p083(a) ordering information part number package internal rom m pd78p083cu(a) 42-pin plastic shrink dip (600 mil) one-time prom m pd78p083gb(a)-3b4 44-pin plastic qfp (10 10 mm) one-time prom m pd78p083gb(a)-3bs-mtx note 44-pin plastic qfp (10 10 mm) one-time prom note under planning caution m m m m m pd78p083gb(a) has two types of packages. (refer to chapter 7. package drawings). consult an necs sales representative for suppliable packages. quality grade part number package quality grades m pd78p083cu(a) 42-pin plastic shrink dip (600 mil) special m pd78p083gb(a)-3b4 44-pin plastic qfp (10 10 mm) special m pd78p083gb(a)-3bs-mtx note 44-pin plastic qfp (10 10 mm) special note under planning please refer to quality grades on nec semiconductor devices (document number c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. deferences between m m m m m pd78p083(a) and m m m m m pd78p083 product m pd78p083(a) m pd78p083 item quality grade special standard package 42-pin plastic shrink dip (600 mil) 42-pin plastic shrink dip (600 mil) 44-pin plastic qfp (10 10 mm) 44-pin plastic qfp (10 10 mm) 42-pin ceramic shrink dip (with window) (600 mil)
3 m pd78p083(a) 78k/0 series development the following shows the 78k/0 series products development. subseries names are shown inside frames. note under planning 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin 100-pin 100-pin 80-pin 80-pin 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series control fip driving iebus tm supported low emi noise version of the pd78078 timer is added to the pd78054 and its external interface is enhanced. rom-less versions of the pd78078 serial i/o of the pd78078 is enhanced and only selected functions are provided. serial i/o-enhanced versions of the pd78054; low emi noise version low emi noise version of the pd78054 uart and d/a converter are added to the pd78014 and i/o is enhanced . a/d-enhanced version of the pd780024 serial i/o-enhanced versions of the pd78018f; low emi noise version low emi noise version of the pd78018f low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities available. a/d converter and 16-bit timer are added to the pd78002. a/d converter is added to the pd78002. basic subseries for control applications on-chip uart, and operable at low voltage (1.8 v). i/o and fip c/d of the pd78044f are enhanced. total display outputs : 53 pins i/o and fip c/d of the pd78044h are enhanced. total display outputs : 48 pins n-ch open-drain i/o is added to the pd78044f. total display outputs : 34 pins basic subseries for fip driving. total display outputs: 34 pins sio of the pd78064 is enhanced, and rom and ram are expanded. low emi noise version of the pd78064 basic subseries for driving lcds and with on-chip uart. iebus controller is added to the pd78054. mass-produced products products under development y subseries supports the i 2 c bus specifications. pd78098 64-pin lv pwm output, lv digital code decoder and hsync counter are incorporated. pd78p0914 pd780308 64-pin 64-pin inverter control a/d-enhanced version of the pd780924 on-chip inverter control circuit and uart incorporated; low emi noise version pd780964 pd780924 lcd driving pd78064b pd78064 pd780208 pd780228 pd78044h pd78044f pd78075b pd78078 pd78070a pd780018 note pd780058 pd78058f pd78054 pd780034 pd780024 pd78014h pd78018f pd78014 pd780001 pd78002 pd78083 pd78075by pd78078y pd78070ay pd780018y note pd780058y note pd78058fy pd78054y pd780034y pd780024y pd78018fy pd78014y pd78002y
4 m pd78p083(a) the following table shows the differences among subseries functions. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32k to 40k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v available m pd78078 48k to 60k m pd78070a 61 2.7 v m pd780018 48k to 60k 2 ch (time division 88 3-wire: 1 ch) m pd780058 24k to 60k 2 ch 2 ch 3 ch (time division 68 1.8 v uart: 1 ch) m pd78058f 48k to 60k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16k to 60k 2.0 v m pd780034 8k to 32k 8 ch 3 ch (uart: 1 ch, time 51 1.8 v m pd780024 8 ch division 3-wire: 1 ch) m pd78014h 2 ch 53 m pd78018f 8k to 60k m pd78014 8k to 32k 2.7 v m pd780001 8k 1 ch 39 m pd78002 8k to 16k 1 ch 53 available m pd78083 8 ch 1 ch (uart: 1 ch) 33 1.8 v inverter m pd780964 8k to 32k 3 ch note 1 ch8 ch 2 ch (uart: 2 ch) 47 2.7 v available control m pd780924 8 ch fip driving m pd780208 32k to 60k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v m pd780228 48k to 60k 3 ch 1 ch 72 4.5 v m pd78044h 32k to 48k 2 ch 1 ch 1 ch 68 2.7 v m pd78044f 16k to 40k 2 ch lcd m pd780308 48k to 60k 2 ch 1 ch 1 ch 1 ch 8 ch 3 ch (time division 57 2.0 v driving uart: 1 ch) m pd78064b 32k 2 ch (uart: 1 ch) m pd78064 16k to 32k iebus m pd78098 32k to 60k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 69 2.7 v available supported lv m pd78p0914 32k 6 ch 1 ch 8 ch 2 ch 54 4.5 v available note 10 bits timer: 1 channel
5 m pd78p083(a) note internal prom and high-speed ram capacities can be changed by setting the memory size switching register (ims). item function internal memory ? prom: 24 kbytes note ? ram high-speed ram: 512 bytes note memory space 64 kbytes general register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) instruction cycles instruction execution time variable function is integrated. 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@5.0-mhz operation with main system clock) instruction set ? 16-bit operation ? multiply/divide (8 bits x 8 bits, 16 bits t 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjust, etc. i/o ports total : 33 ? cmos input : 1 ? cmos input/output : 32 a/d converter ? 8-bit resolution x 8 channels serial interface ? 3-wired serial i/o/uart mode selectable: 1 channel timer ? 8-bit timer/event counter: 2 channels ? watchdog timer: 1 channel timer output 2 pins (8-bit pwm output enable) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, and 5.0 mhz (@ 5.0-mhz operation with main system clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, and 9.8 khz (@ 5.0-mhz operation with main system clock) vectored-interrupt maskable internal : 8 external : 3 source non-maskable internal : 1 software internal : 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85c packages ? 42-pin plastic shrink dip (600 mil) ? 44-pin plastic qfp (10 10 mm) function description
6 m pd78p083(a) pin configurations (top view) (1) normal operating mode ? 42-pin plastic shrink dip (600 mil) m pd78p083cu(a) cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . v ss av ref p54 p53 p52 p51 p50 p100/ti5/to5 p101/ti6/to6 p70/r x d/si2 p71/t x d/so2 p72/asck/sck2 p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ss p55 av dd p56 p57 p30 p31 p32 p33 p34 p35/pcl p36/buz p37 p00 p01/intp1 p02/intp2 p03/intp3 reset v pp x2 x1 v dd 42 22 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
7 m pd78p083(a) ? 44-pin plastic qfp (10 x 10 mm) m pd78p083gb(a)-3b4, pd78p083gb(a)-3bs-mtx note note under planning cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . 4. connect nc pin to v ss for noise protection (it can be left open). p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 p72/asck/sck2 p71/t x d/so2 p70/r x d/si2 p101/ti6/to6 p100/ti5/to5 p03/intp3 p02/intp2 p01/intp1 p00 p37 p36/buz p35/pcl p34 p33 p32 nc p50 p51 p52 p53 p54 v ss p55 p56 p57 p30 p31 p11/ani1 p10/ani0 av ss av ref av dd v dd x1 x2 v pp reset nc 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
8 m pd78p083(a) ani0 to ani7 : analog input pcl : programmable clock asck : asynchronous serial clock reset : reset av dd : analog power supply r x d : receive data av ref : analog reference voltage sck2 : serial clock av ss : analog ground si2 : serial input buz : buzzer clock so2 : serial output intp1 to intp3 : interrupt from peripherals ti5, ti6 : timer input nc : non-connection to5, to6 : timer output p00 to p03 : port 0 t x d : transmit data p10 to p17 : port 1 v dd : power supply p30 to p37 : port 3 v pp : programming power supply p50 to p57 : port 5 v ss : ground p70 to p72 : port 7 x1, x2 : crystal (main system clock) p100, p101 : port 10
9 m pd78p083(a) (2) prom programming mode ? 42-pin plastic shrink dip (600 mil) m pd78p083cu(a) cautions 1. (l): individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open. v ss v ss a4 a3 a2 a1 a0 a10 a11 a12 a13 a14 d7 d6 d5 d4 d3 d2 d1 d0 v ss a5 v dd a6 a7 oe ce pgm a8 a9 reset v pp open v dd 42 22 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ? ? ? ? ? ? ? ? (l) (l) (l)
10 m pd78p083(a) cautions 1. (l): individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: leave open. a0 to a14 : address bus reset : reset ce : chip enable v dd : power supply d0 to d7 : data bus v pp : programming power supply oe : output enable v ss : ground pgm : program ? 44-pin plastic qfp (10 x 10 mm) pd78p083gb(a)-3b4, pd78p083gb(a)-3bs-mtx note note under planning d2 d3 d4 d5 d6 d7 a14 a13 a12 a11 a10 a9 a8 (l) (l) (l) (l) (l) pgm a0 a1 a2 a3 a4 v ss a5 a6 a7 oe ce d1 d0 v ss v ss v dd v dd open v pp reset 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 ? ? ? ? ? ? ? ?
11 m pd78p083(a) block diagram p100/ti5/to5 p101/ti6/to6 si2/r x d/p70 so2/t x d/p71 sck2/asck/p72 ani0/p10- ani7/p17 av dd av ss av ref intp1/p01- intp3/p03 buz/p36 pcl/p35 port 0 port 1 port 3 port 5 port 7 port 10 system control 8-bit timer/ event counter 5 buzzer output interrupt control a/d converter serial interface 2 watchdog timer clock output control 8-bit timer/ event counter 6 78k/0 cpu core prom (24 kbytes) data memory (512 bytes) p00 p01-p03 p10-p17 p30-p37 p50-p57 p70-p72 p100, p101 reset x1 x2 v dd v ss v pp
12 m pd78p083(a) contents 1. differences between the m pd78p083(a) and mask rom versions ....................... 13 2. pin functions ............................................................................................................................. 14 2.1 pins in normal operating mode ............................................................................................................ 14 2.2 pins in prom programming mode ....................................................................................................... 16 2.3 pin input/output circuits and recommended connection of unused pins .................................. 16 3. internal memory size switching register (ims) ........................................................ 18 4. prom programming ................................................................................................................. 19 4.1 operating modes ..................................................................................................................................... 19 4.2 prom write procedure .......................................................................................................................... 21 4.3 prom read procedure .......................................................................................................................... 25 5. one-time prom version screening ................................................................................... 26 6. electrical specifications .................................................................................................. 27 7. package drawings ................................................................................................................. 45 8. recommended soldering conditions ............................................................................. 48 appendix a. development tools ........................................................................................... 49 appendix b. related documents ........................................................................................... 51
13 m pd78p083(a) parameter pd78p083(a) mask rom versions internal rom type one-time prom/eprom mask rom internal rom capacity 24 kbytes pd78081(a) : 8 kbytes pd78082(a) : 16 kbytes internal high-speed ram capacity 512 bytes pd78081(a) : 256 bytes pd78082(a) : 384 bytes internal rom and internal high-speed enable note disable ram capacity change by memory size switching register (ims) ic pin no yes v pp pin yes no electrical specifications refer to a data sheet of each product 1. differences between the m pd78p083(a) and mask rom versions the m pd78p083(a) is a single-chip microcontroller with an on-chip one-time prom. setting the memory size switching register (ims) makes the functions except the prom specification identical to the mask rom versions. table 1-1 shows differences between the prom version ( m pd78p083(a)) and mask rom versions ( m pd78081(a) and m pd78082(a)). table 1-1. differences between the m m m m m pd78p083(a) and mask rom versions note the internal prom becomes 24 kbytes and the internal high-speed ram becomes 512 bytes by the reset input.
14 m pd78p083(a) pin name input/output function after reset alternate function p00 input port 0 input only input p01 input/output 4-bit input/output port input/output is specifiable input intp1 p02 bit-wise. when used as the intp2 p03 input port, it is possible to intp3 connect a pull-up resistor by software. p10 to p17 input/output port 1 input ani0 to ani7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. note p30-p34 input/output port 3 input p35 8-bit input/output port pcl p36 input/output is specifiable bit-wise. buz p37 when used as the input port, it is possible to connect a pull-up resistor by software. p50 to p57 input/output port 5 input 8-bit input/output port can drive up to seven leds directly. input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. p70 input/output port 7 input si2/rxd p71 3-bit input/output port so2/txd p72 input/output is specifiable bit-wise. sck2/asck when used as the input port, it is possible to connect a pull-up resistor by software. p100 input/output port 10 input ti5/to5 p101 2-bit input/output port ti6/to6 input/output is specifiable bit-wise. when used as the input port, it is possible to connect a pull-up resistor by software. 2. pin functions 2.1 pins in normal operating mode (1) port pins note when p10/ani0-p17/ani7 pins are used as the analog inputs for the a/d converter, set the port 1 to the input mode. the on-chip pull-up resistor is automatically disabled.
15 m pd78p083(a) (2) non-port pins pin name input/output function after reset alternate function intp1 input external interrupt input by which the active edge (rising edge, input p01 intp2 falling edge, or both rising and falling edges) can be specified. p02 intp3 p03 si2 input serial interface serial data input. input p70/rxd so2 output serial interface serial data output. input p71/txd sck2 input/output serial interface serial clock input/output. input p72/asck rxd input asynchronous serial interface serial data input. input p70/si2 txd output asynchronous serial interface serial data output. input p71/so2 asck input asynchronous serial interface serial clock input. input p72/sck2 ti5 input external count clock input to 8-bit timer (tm5). input p100/to5 ti6 external count clock input to 8-bit timer (tm6). p101/to6 to5 output 8-bit timer output. input p100/ti5 to6 p101/ti6 pcl output clock output. (for main system clock trimming) input p35 buz output buzzer output. input p36 ani0 to ani7 input a/d converter analog input. input p10 to p17 av ref input a/d converter reference voltage input. C C av dd C a/d converter analog power supply. connected to v dd .CC av ss C a/d converter ground potential. connected to v ss .CC reset input system reset input. C C x1 input main system clock oscillation crystal connection. C C x2 C CC v dd C positive power supply. C C v pp C high-voltage applied during program write/verification. C C connected directly to v ss in normal operating mode. v ss C ground potential. C C nc C does not internally connected. connect to v ss .CC (it can be left open)
16 m pd78p083(a) pin name input/output input/output recommended connection for unused pins circuit type p00 2 input connect to v ss . p01/intp1 8-a input/output independently connect to v ss via a resistor. p02/intp2 p03/intp3 p10/ani0 to p17/ani7 11 input/output independently connect to v dd or v ss via p30 to p32 5-a a resistor. p33, p34 8-a p35/pcl 5-a p36/buz p37 p50 to p57 5-a p70/si2/rxd 8-a p71/so2/txd 5-a p72/sck2/asck 8-a p100/ti5/to5 8-a p101/ti6/to6 reset 2 input C av ref C C connect to v ss . av dd connect to v dd . av ss connect to v ss . v pp connect directly to v ss . nc connect to v ss (can leave open) 2.2 pins in prom programming mode pin name input/output function reset input prom programming mode setting when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, this chip is set in the prom programming mode. v pp input prom programming mode setting and high-voltage applied during program write/verification. a0 to a14 input address bus d0-d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode. v dd positive power supply v ss ground potential 2.3 pin input/output circuits and recommended connection of unused pins types of input/output circuits of the pins and recommeded connection of unused pins are shown in table 2-1. for the configuration of each type of input/output circuit, see figure 2-1. table 2-1. type of input/output circuit of each pin
17 m pd78p083(a) figure 2-1. types of pin input/output circuits type 2 in type 8-a pull-up enable data output disable v dd p-ch n-ch p-ch in/out v dd type 11 pull-up enable data output disable v dd p-ch n-ch p-ch in/out v dd type 5-a input enable schmitt-triggered input with hysteresis characteristics pull-up enable data output disable input enable n-ch v dd p-ch in/out v dd p-ch p-ch n-ch v ref (threshold voltage) comparator +
18 m pd78p083(a) 3. internal memory size switching register (ims) this is a register to disable use of part of internal memories by software. by setting this memory size switching register (ims), it is possible to get the same memory mapping as that of the mask rom versions with a different internal memory (rom, ram). ims is set with an 8-bit memory manipulation instruction. reset input sets ims to 46h. figure 3-1. internal memory size switching register format ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 7654321 0 symbol ims address r/w fff0h 46h after reset r/w selection of internal rom3 rom2 rom1 rom0 rom capacity 00108 kbytes 010016 kbytes 011024 kbytes other than above setting prohibited table 3-1 shows the setting values of ims which make the memory mapping the same as that of the mask rom version. table 3-1. internal memory size switching register setting values selection of internal ram2 ram1 ram0 high-speed ram capacity 0 1 0 512 bytes 0 1 1 384 bytes 1 0 0 256 bytes other than above setting prohibited target mask rom versions ims setting value pd78081(a) 82h pd78082(a) 64h
19 m pd78p083(a) pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit x h h high-impedance xll read +5 v +5 v l l h data output output disable l h x high-impedance standby h x x high-impedance x : l or h 4. prom programming the pd78p083(a) has an internal 24-kbyte prom as a program memory. for programming, set the prom programming mode with the v pp and reset pins. for the connection of unused pins, refer to pin configura- tions (top view) (2) prom programming mode. caution programs must be written in addresses 0000h to 5fffh (the last address 5fffh must be specified). they cannot be written by a prom programmer which cannot specify the write address. 4.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 4-1 when the ce, oe, and pgm pins are set as shown. further, when the read mode is set, it is possible to read the contents of the prom. table 4-1. operating modes of prom programming
20 m pd78p083(a) (1) read mode read mode is set if ce = l, oe = l is set. (2) output disable mode data output becomes high-impedance, and is in the output disable mode, if oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd78p083(a)s are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h, oe = h. then, program verification can be performed, if ce = l, oe = l are set. if programming is not performed by a one-time program pulse, x times (x - 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1-ms program pulse (active low) is applied to the pgm pin with ce = l, oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x times (x - 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, oe = l are set. in this mode, check if a write operation is performed correctly after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin, and d0-d7 pins of multiple m pd78p083(a)s are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high.
21 m pd78p083(a) 4.2 prom write procedure figure 4-1. page program mode flow chart g = start address n = program last address start address = g v dd = +6.5 v, v pp = +12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 x = 10 ? address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 0.1-ms program pulse verify 4 bytes verify all bytes write end defective product
22 m pd78p083(a) figure 4-2. page program mode timing a2-a14 a0, a1 d0-d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input
23 m pd78p083(a) figure 4-3. byte program mode flow chart g = start address n = program last address start address = g v dd = +6.5 v, v pp = +12.5 v x = 0 x = x + 1 address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 x = 10 ? 0.1-ms program pulse verify verify all bytes write end defective product
24 m pd78p083(a) figure 4-4. byte program mode timing cautions 1. v dd should be applied before v pp and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while +12.5 v is being applied to v pp . program data input data output program verify a0-a14 d0-d7 v pp v pp v dd v dd + 1.5 v dd v ih v il v dd ce v ih v il pgm v ih v il oe
25 m pd78p083(a) a0-a14 ce (input) oe (input) d0-d7 hi-z address input data output hi-z 4.3 prom read procedure the contents of prom are readable to the external data bus (d0-d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the v pp pin, and connect all other unused pins as shown in pin configurations (top view) (2) prom programming mode. (2) supply +5 v to the v dd and v pp pins. (3) input address of read data into the a0 to a14 pins. (4) read mode (5) output data to d0 to d7 pins. the timings of the above steps (2) to (5) are shown in figure 4-5. figure 4-5. prom read timings
26 m pd78p083(a) 5. one-time prom version screening the one-time prom version ( m pd78p083cu(a), 78p083gb(a)-3b4, 78p083gb(a)-3bs-mtx note ) cannot be tested completely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the condition below. note under planning storage temperature storage time 125c 24 hours nec offers for an additional fee one-time prom writing to marking, screening, and verify for products designated as qtop microcontroller. a fee-charged service for the m pd78p083(a) is under planning. consult an nec sales representative for details.
27 m pd78p083(a) parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v av dd C0.3 to v dd + 0.3 v av ref C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 C0.3 to v dd + 0.3 v i2 a9 prom programming mode C0.3 to +13.5 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pins av ss C 0.3 to av ref + 0.3 v output current, high i oh per pin C10 ma total for p10 to p17, p50 to p54, C15 ma p70 to p72, p100, p101 total for p01 to p03, p30 to p37, C15 ma p55 to p57 output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total for p50 to p54 peak value 100 ma r.m.s. value 70 ma total for p55 to p57 peak value 100 ma r.m.s. value 70 ma total for p10 to p17, peak value 50 ma p70 to p72, p100, p101 r.m.s. value 20 ma total for p01 to p03, peak value 50 ma p30 to p37 r.m.s. value 20 ma operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c 6. electrical specifications absolute maximum ratings (t a = 25c) note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution if the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product may be degraded. the absolute maximum ratings are therefore the rated values that may, if exceeded, physically damage the product. be sure to use the product with all the absolute maximum ratings observed. remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
28 m pd78p083(a) resonator recommended parameter test conditions min. typ. max. unit circuit ceramic oscillation frequency v dd = oscillation voltage range 1.0 5.0 mhz resonator (fx) note 1 oscillation stabilization after v dd came to min. 4 ms time note 2 of oscillation voltage range crystal oscillation frequency 1.0 5.0 mhz resonator (fx) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 10 ms time note 2 30 external clock x1 input frequency 1.0 5.0 mhz (fx) note 1 x1 input high- and 85 500 ns low-level widths (t xh , t xl ) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v. 15 pf i/o capacitance c io f = 1 mhz, p01 to p03, p10 to p17, 15 pf unmeasured pins p30 to p37, p50 to p57, returned to 0 v. p70 to p72, p100, p101 capacitance (t a = 25c, v dd = v ss = 0 v) remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. main system clock oscillator characteristics (t a = C40 to +85c, v dd = 1.8 to 5.5 v) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac character- istics . 2. time required for oscillation to stabilize after a reset or the stop mode has been released. caution when using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figures as follows to avoid adverse influences on the wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring over other signal lines. ? do not route the wiring in the vicinity of lines through which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . ? do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit. v pp c1 x1 c2 x2 v pp c1 x1 c2 x2 x2 x1 pd74hcu04 m
29 m pd78p083(a) parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p10 to p17, p30 to p32, v dd = 2.7 to 5.5 v 0.7v dd v dd v p35 to p37, p50 to p57, p71 0.8v dd v dd v v ih2 p00 to p03, p33, p34, v dd = 2.7 to 5.5 v 0.8v dd v dd v p70, p72, p100, p101, reset 0.85v dd v dd v v ih3 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd C 0.2 v dd v input voltage, low v il1 p10 to p17, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3v dd v p35 to p37, p50 to p57, p71 0 0.2v dd v v il2 p00 to p03, p33, p34, v dd = 2.7 to 5.5 v 0 0.2v dd v p70, p72, p100, p101, reset 0 0.15v dd v v il3 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v output voltage, high v oh v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v i oh = C100 a v dd C 0.5 v output voltage, low v ol p50 to p57 v dd = 2.0 to 4.5 v, 0.8 v i ol = 10 ma v dd = 4.5 to 5.5 v, 0.4 2.0 v i ol = 15 ma p01 to p03, p10 to p17, v dd = 4.5 to 5.5 v, 0.4 v p30 to p37, p70 to p72, i ol = 1.6 ma p100, p101 i ol = 400 m a 0.5 v input-leak current, high i lih1 v in = v dd p00 to p03, p10 to p17, 3 m a p30 to p37, p50 to p57, p70 to p72, p100, p101, reset i lih2 x1, x2 20 m a input-leak current, low i lil1 v in = 0 v p00 to p03, p10 to p17, C3 m a p30 to p37, p50 to p57, p70 to p72, p100, p101, reset i lil2 x1, x2 C20 a output leak current, high i loh v out = v dd 3 m a output leak current, low i lol v out = 0 v C3 m a software pull-up resistor r v in = 0 v p01 to p03, p10 to p17, 15 40 90 k w p30 to p37, p50 to p57, p70 to p72, p100, p101 dc characteristics (t a = C40 to +85c, v dd = 1.8 to 5.5 v) remark unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
30 m pd78p083(a) parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 5.0-mhz crystal v dd = 5.0 v 10% note 4 5.4 16.2 ma oscillation operating v dd = 3.0 v 10% note 5 0.8 2.4 ma mode (f xx = 2.5 mhz) note 2 v dd = 2.0 v 10% note 5 0.45 1.35 ma 5.0-mhz crystal oscillation v dd = 5.0 v 10% note 4 9.5 28.5 ma operating mode v dd = 3.0 v 10% note 5 1.0 3.0 ma (f xx = 5.0 mhz) note 3 i dd2 5.0-mhz crystal oscillation v dd = 5.0 v 10% 1.4 4.2 ma halt mode v dd = 3.0 v 10% 0.5 1.5 ma (f xx = 2.5 mhz) note 2 v dd = 2.0 v 10% 280 840 m a 5.0-mhz crystal oscillation v dd = 5.0 v 10% 1.6 4.8 ma halt mode v dd = 3.0 v 10% 0.65 1.95 ma (f xx = 5.0 mhz) note 3 i dd3 stop mode v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a v dd = 2.0 v 10% 0.05 10 m a dc characteristics (t a = C40 to +85c, v dd = 1.8 to 5.5 v) notes 1. not including av ref , av dd currents or port currents (including current flowing into internal pull-up resistors). 2. f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h). 3. f xx = f x operation (when oscillation mode selection register (osms) is set to 01h). 4. high-speed mode operation (when processor clock control register (pcc) is set to 00h). 5. low-speed mode operation (when processor clock control register (pcc) is set to 04h). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency
31 m pd78p083(a) ac characteristics (1) basic operation (t a = C40 to +85c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy f xx = f x /2 note1 v dd = 2.7 to 5.5 v 0.8 64 m s (minimum instruction 2.0 64 m s execution time) f xx = f x / note2 3.5 v - v dd - 5.5 v 0.4 32 m s 2.7 v - v dd < 3.5 v 0.8 32 m s ti5, ti6 f ti v dd = 4.5 to 5.5 v 0 4 mhz input frequency 0 275 khz ti5, ti6 input high-/ t tih ,v dd = 4.5 to 5.5 v 100 ns low-level widths t til 1.8 m s interrupt input high-/ t inth ,v dd = 2.7 to 5.5 v 10 m s low-level widths t intl 20 m s reset low-level width t rsl v dd = 2.7 to 5.5 v 10 m s 20 m s notes 1. when oscillation mode selection register (osms) is set to 00h. 2. when osms is set to 01h. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency t cy vs v dd t cy vs v dd (main system clock f xx = f x /2 operation) (main system clock f xx = f x operation) 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] cycle time t cy [ s] m operation guaranteed range
32 m pd78p083(a) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy2 4.5 v - v dd - 5.5 v 800 ns 2.7 v - v dd < 4.5 v 1600 ns 2.0 v - v dd < 2.7 v 3200 ns 4800 ns sck2 high-/low-level width t kh2 , 4.5 v - v dd - 5.5 v 400 ns t kl2 2.7 v - v dd < 4.5 v 800 ns 2.0 v - v dd < 2.7 v 1600 ns 2400 ns si2 setup time (to sck2 ? )t sik2 v dd = 2.0 to 5.5 v 100 ns 150 ns si2 hold time (from sck2 ? )t ksi2 400 ns sck2 ? ? so2 t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output delay time 500 ns sck2 rise, fall time t r2 , 1000 ns t f2 (2) serial interface (t a = C40 to +85c, v dd = 1.8 to 5.5 v) (a) 3-wired serial i/o mode (sck2 internal clock output) note c is the sck2, so2 output line load capacitance. (b) 3-wired serial i/o mode (sck2 external clock input) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy1 4.5 v - v dd - 5.5 v 800 ns 2.7 v - v dd < 4.5 v 1600 ns 2.0 v - v dd < 2.7 v 3200 ns 4800 ns sck2 high-/low-level width t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2C50 ns t kl1 t kcy1 /2C100 ns si2 setup time (to sck2 ? )t sik1 4.5 v - v dd - 5.5 v 100 ns 2.7 v - v dd < 4.5 v 150 ns 2.0 v - v dd < 2.7 v 300 ns 400 ns si2 hold time (from sck2 ? )t ksi1 400 ns sck2 ? ? so2 t kso1 c = 100 pf note 300 ns output delay time note c is the so2 output line load capacitance.
33 m pd78p083(a) parameter symbol test conditions min. typ. max. unit asck cycle time t kcy3 4.5 v - v dd - 5.5 v 800 ns 2.7 v - v dd < 4.5 v 1600 ns 2.0 v - v dd < 2.7 v 3200 ns 4800 ns asck high-/low-level width t kh3 , 4.5 v - v dd - 5.5 v 400 ns t kl3 2.7 v - v dd < 4.5 v 800 ns 2.0 v - v dd < 2.7 v 1600 ns 2400 ns transfer rate 4.5 v - v dd - 5.5 v 39063 bps 2.7 v - v dd < 4.5 v 19531 bps 2.0 v - v dd < 2.7 v 9766 bps 6510 bps asck rise, fall time t r3 , 1000 ns t f3 parameter symbol test conditions min. typ. max. unit transfer rate 4.5 v - v dd - 5.5 v 78125 bps 2.7 v - v dd < 4.5 v 39063 bps 2.0 v - v dd < 2.7 v 19531 bps 9766 bps (c) uart mode (dedicated baud rate generator output) (d) uart mode (external clock input)
34 m pd78p083(a) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ac timing test point (excluding x1 input) clock timing ti timing 1/f ti t til t tih ti5, ti6 1/f x t xl t xh v ih3 (min.) v il3 (max.) x1 input
35 m pd78p083(a) serial transfer timing 3-wired serial i/o mode: t kso1, 2 sck2 si2 so2 input data output data t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 t r2 t f2 uart mode (external clock input): asck t kl3 t kh3 t r3 t f3 t kcy3
36 m pd78p083(a) parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit total error note 2.7 v - av ref - av dd 1.4 % conversion time t conv 19.1 200 m s sampling time t samp 12/f xx m s analog input voltage v ian av ss av ref v reference voltage av ref 2.7 av dd v av ref -av ss resistance r airef 414 k w a/d converter characteristics (t a = C40 to +85c, av dd = v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) note excluding quantization error (1/2 lsb). shown as a percentage of the full scale value. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency
37 m pd78p083(a) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v data retention supply current i dddr v dddr = 1.8 v 0.1 10 m a release signal set time t srel 0 m s oscillation stabilization wait t wait release by reset 2 17 /f x ms time release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85c) note 2 12 /f xx or 2 14 /f xx to 2 17 /f xx can be selected by bit 0 to bit 2 (osts0 to osts2) of oscillation stabilization time selection register (osts). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode released by reset) data retention timing (standby release signal: stop mode released by interrupt request signal) stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel
38 m pd78p083(a) interrupt input timing reset input timing intp1-intp3 t intl t inth reset t rsl
39 m pd78p083(a) parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh1 v oh1 i oh = C1 ma v dd C 1.0 v v oh2 v oh2 i oh = C100 m av dd C 0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 - v in - v dd C10 +10 m a output leakage current i lo i lo 0 - v out - v dd , oe = v ih C10 +10 m a v pp supply voltage v pp v pp v dd C 0.6 v dd v dd + 0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh v oh i oh = C1 ma v dd C 1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 - v in - v dd C10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma prom programming characteristics dc characteristics ( 1) prom write mode (t a = 25 5?c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) (2) prom read mode (t a = 25 5?c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) note corresponding m pd27c1001a symbol.
40 m pd78p083(a) parameter symbol symbol note test conditions min. typ. max. unit address setup time (to pgm ? )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to pgm ? )t ces t ces 2 m s input data setup time (to pgm ? )t ds t ds 2 m s address hold time (from oe ? )t ah t ah 2 m s input data hold time t dh t dh 2 m s (from pgm ? ) oe ? ? data output float t df t df 0 250 ns delay time v pp setup time (to pgm ? )t vps t vps 1.0 ms v dd setup time (to pgm ? )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms oe ? ? valid data delay time t oe t oe 1 m s oe hold time t oeh 2 m s parameter symbol symbol note test conditions min. typ. max. unit address setup time (to oe ? )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to oe ? )t ces t ces 2 m s input data setup time (to oe ? )t ds t ds 2 m s address hold time (from oe ? )t ah t ah 2 m s t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe ? )t dh t dh 2 m s oe ? ? data output float t df t df 0 250 ns delay time v pp setup time (to oe ? )t vps t vps 1.0 ms v dd setup time (to oe ? )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms oe ? ? valid data delay time t oe t oe 1 m s oe pulse width during data t lw t lw 1 m s latching pgm setup time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s ac characteristics (1) prom write mode (a) page program mode (t a = 25 5?c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) (b) byte program mode (t a = 25 5?c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) note corresponding m pd27c1001a symbol.
41 m pd78p083(a) parameter symbol symbol note test conditions min. typ. max. unit address ? ? data output float t acc t acc ce = oe = v il 800 ns delay time ce ? ? valid output delay time t ce t ce oe = v il 800 ns oe ? ? valid output delay time t oe t oe ce = v il 200 ns oe ? ? data output float t df t df ce = v il 060ns delay time address ? data hold time t oh t oh ce = oe = v il 0ns (2) prom read mode (t a = 25 5?c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol test conditions min. typ. max. unit prom programming mode setup time tsma 10 m s note corresponding m pd27c1001a symbol. (3) prom programming mode (t a = 25?c, v ss = 0 v)
42 m pd78p083(a) prom write mode timing (page program mode) a2-a14 a0, a1 d0-d7 v pp v dd v pp v dd +1.5 v dd v dd v ih v il ce v ih v il pgm v ih v il oe t lw t pw t ceh t as t ds t vps t vds hi-z hi-z data input t pgms t dh t ahl t ahv t df t oe data output t ah hi-z t ces t oeh t oes page data latch page program program verify
43 m pd78p083(a) notes 1. if you want to read within the range of t acc , make the oe input delay time from the fall of ce a maximum of t acc C t oe . 2. t df is the time from when either oe or ce first reaches v ih . prom write mode timing (byte program mode) cautions 1. v dd should be applied before v pp , and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while + 12.5 v is being applied to v pp . prom read mode timing a0-a14 v ih ce v il v ih oe v il d0-d7 data output effective address hi-z hi-z t ce t acc note 1 t df note 2 t oh t oe note 1 a0-a14 v pp d0-d7 v pp v dd v dd +1.5 v dd v dd v ih ce v il v ih pgm v il v ih oe v il t vps t as t ds t vds t ces t pw t oes t oe t oeh t dh hi-z hi-z hi-z t df t ah program verify program data input data output
44 m pd78p083(a) prom programming mode setting timing t sma effective address v dd 0 v dd v dd 0 v pp reset a0-a14

▲Up To Search▲

Price & Availability of PD78P083A

	To Download PD78P083A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .